1. Field of the Invention
The present invention relates to a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor, and a method of manufacturing the same. As used herein, the term xe2x80x9cMOS transistorxe2x80x9d denotes a field effect transistor having a MOS structure, and is also used as the concept including the case where not only an oxide but also another insulator is employed as a gate insulating film.
2. Description of the Background Art
FIG. 30 is a cross section illustrating the step of forming a gate electrode in a conventional method of manufacturing a MOS transistor. In the surface of a semiconductor substrate 1, an active region is defined by an element isolation region 9, such as a trench isolation. A gate insulating film 2 is then formed on the surface of the semiconductor substrate 1 by performing thermal oxidation.
Subsequently, a stacked structure comprising a polysilicon layer 3, silicide layer 4, and a nitride film 5 that functions later as a hard mask, is temporarily formed on the entire surface, and an anti-reflection coating film (not shown) is stacked thereon. After a resist (not shown) is applied to the entire surface, a pattern transfer and its development are performed so that the resist is of a predetermined shape. By using the resulting resist pattern as a mask, the nitride film 5 is formed in a predetermined shape by etching. By using the resulting nitride film 5 as a hard mask, an etching is conducted so that the silicide layer 4 and polysilicon layer 3 are made into the same shape as the nitride film 5, when viewed from above, thereby obtaining the structure shown in FIG. 30.
When an oxide film is employed as a gate insulating film 2, the etching of the polysilicon layer 3 can be performed in a high etching selective ratio to the gate insulating film 2. Therefore, even when the polysilicon layer 3 is further etched from the state that it remains only beneath the nitride film 5, it is able to reduce the amount of etching of the gate insulating film 2.
Thus, the feature that the area making a direct contact with a gate insulating film is formed with polysilicon, enables to reduce the difference in the work function with silicon, as compared to the case where an NMOS transistor and PMOS transistor are both formed with a single metal or silicide.
Recently, as semiconductor devices have lower operating current and higher speed, its gate insulating film becomes thinner. Further, it is intended that a gate nitride film having a higher dielectric constant is substituted for a gate oxide film.
However, the etching selective ratio of a nitride film to polysilicon cannot be made so high as that of an oxide film to polysilicon. Therefore, the adoption of a nitride film as a gate insulating film 2 and the adoption of polysilicon as the portion of a gate electrode making a direct contact with the gate insulating film 2 have caused a drawback requiring a rigid control during etching for modifying the polysilicon as the gate electrode.
FIGS. 31 and 32 are cross sections illustrating an aspect that can occur in the event of failure of the rigid control of the above etching. That is, FIG. 31 shows the state that a gate insulating film 2 used instead of the gate oxide film 21 in FIG. 30 is broken during the etching of polysilicon, and an etchant reaches the semiconductor substrate 1, thereby forming a void 11 in the semiconductor substrate 1. Even if an oxide film is employed as the gate insulating film 2, such a problem becomes significant when the thickness of the oxide film is reduced.
Even if the etchant does not reach the semiconductor substrate 1, when the gate insulating film 2 becomes thin, an etching induced damage remains in the semiconductor substrate 1. FIG. 32 shows the state that an etching induced damage 12 occurs in the semiconductor substrate 1. The etching induced damage 12 acts as the trap of carrier. For instance, in an LDD (Lightly Doped Drain) structure, an extension region is formed which is continuous with a source/drain, and has a lower impurity concentration than that of the source/drain. This trap reduces the carrier concentration, in particular, the carrier concentration in the extension region, and also increases the parasitic resistance of a transistor. An increase in parasitic resistance causes an increase in heat generation and a reduction in operating speed, on an integrated circuit.
According to a first aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type; (b) forming a first conductive layer on the gate insulating film; (c) selectively forming a second conductive layer on the first conductive layer; (d) selectively imparting an insulating property to the first conductive layer by using the second conductive layer as a mask, to obtain an insulating layer; and (e) forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left in the step (d).
According to a second aspect, the method of the first aspect is characterized in that the first conductive layer is composed of a doped semiconductor, and the doped semiconductor is selectively oxidized in the step (d), the method further comprising the step, after the step (e), of: (f) performing an etching of the insulating layer and the gate insulating film so that these are selectively removed to expose the source/drain regions.
Preferably, the method of the second aspect further comprises the step of: (g) performing a silicidation of the source/drain regions exposed in the step (f).
According to a third aspect, the method of the second aspect further comprises the step, after the step (c) and before the step (d), of: (g) implanting impurities to the surface of the semiconductor substrate by using the second conductive layer as a mask, so as to form a pair of extension regions of the second conductivity type in the surface of the semiconductor substrate.
According to a fourth aspect, the method of the second aspect is characterized in that the second conductivity layer is composed of metal, and, in the step (d) an oxidation is conducted in an oxidizing atmosphere having a reducing component.
Preferably, the reducing component includes hydrogen.
According to a fifth aspect, the method of the first aspect further comprises the step, after the step (c) and before the step (d), of: (f) forming a coating layer covering the second conductive layer and the first conductive layer, and is characterized in that in the step (d), insulating property is imparted to said coating layer and said coating layer becomes part of the insulating layer.
According to a sixth aspect, the method of the fifth aspect is characterized in that the first conductive layer is composed of a first semiconductor doped, that the coating layer is composed of a material that is an oxidizable material, and that the first semiconductor and the material are oxidized in the step (d), the method further comprising the step, after the step (e), of: (f) selectively removing the insulating film and the gate insulating film to expose the source/drain region.
According to a seventh aspect, the method of the sixth aspect further comprises the step, after the step (d) and before the step (f), of: (g) implanting impurities to the surface of the semiconductor substrate by using, as a mask, the second conductive layer and the coating layer present on the side of the second conductive layer, thereby to form a pair of extension regions of the second conductivity type in the surface of the semiconductor substrate.
According to an eighth aspect, the method of the sixth aspect is characterized in that the second conductive layer is composed of metal, and that the coating layer is composed of a second semiconductor, the method further comprising the step, after the step (d) and before the step (f), of: (g) performing a heat treatment for forming a silicide layer at the interface between the second conductive layer and the coating layer.
According to a ninth aspect, a method of manufacturing a semiconductor device comprises the steps of: (a) forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type; (b) forming a first conductive layer on the gate insulating film; (c) selectively forming a dummy gate on the first conductive layer; (d) selectively imparting an insulating property to the first conductive layer by using the dummy gate as a mask, thereby to obtain a first insulating layer; (e) forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left in the step (d); (f) forming a second insulating layer on the structure resulting from the steps (a) to (e); (g) polishing the second insulating layer from its surface, to expose the dummy gate; (h) removing the dummy gate to form a recess surrounded by the second insulating layer, the first conductive layer left in the step (d), and the first insulating layer; and (i) providing in the recess a third conductive layer making contact with the first conductive layer.
Preferably, in the method of the ninth aspect, the step (i) includes: (i-1) forming the third conductive layer on the second insulating layer, filling the recess; and (i-2) polishing the third conductive layer from its surface, to expose the second insulating layer.
According to a tenth aspect, the method of the ninth aspect is characterized in that the first conductive layer is composed of a doped semiconductor, and that the semiconductor is selectively oxidized in the step (d), the method further comprising the step, after the step (e), of: (j) performing an etching of the insulating layer and the gate insulating film so that these are selectively removed to expose the source/drain region.
Preferably, the method of the tenth aspect further comprises the step of: (k) performing a silicidation of the source/drain region exposed in the step (j).
According to an eleventh aspect, the method of the tenth aspect further comprises the step, after the step (c) and before the step (d), of: (k) implanting impurities to the surface of the semiconductor substrate by using the dummy gate as a mask, thereby to form a pair of extension regions of the second conductivity type in the surface of the semiconductor substrate.
Preferably, in the method of the eleventh aspect, the step (e) includes: (e-1) forming a sidewall on the side of the dummy gate; and (e-2) implanting impurities to the surface of the semiconductor substrate by using the dummy gate and the sidewall, as mask.
According to a twelfth aspect, a semiconductor device comprises: a gate insulating film selectively provided on a surface of a semiconductor substrate of a first conductivity type; a conductor facing the surface through the gate insulating film; an interposing layer disposed between the conductor and the gate insulating film, the interposing layer having an insulating property at least beneath the end of the conductor, and having a conductivity at least beneath the center of the conductor; and a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, the source/drain regions being disposed in an area of the surface which is exposed by the absence of the gate insulating film, and sandwiching therebetween the surface underlying the conductor.
Preferably, the semiconductor device of the twelfth aspect further comprises a pair of extension regions of the second conductivity type disposed in the surface, the extension regions extending closer to an area underlying the center of the conductor, than does the source/drain region.
More preferably, the semiconductor device of the twelfth aspect further comprises a silicide layer disposed in the surface of the source/drain region.
With the method of the first or fifth aspect, the first conductive layer is not etched but is left only below the second conductive layer by imparting insulating property in a self-aligned manner, by using the second conductive layer as a mask. The second conductive layer and the first conductive layer left therebelow cooperate in functioning as a gate electrode. It is therefore able to reliably form a gate electrode even when using, as a gate insulating film, a material with which it is unable to have a high etching selective ratio to the first conductive layer.
With the method of the second or sixth aspect, the insulating layer and gate insulating film are etched in the step (f). This permits a reliable formation of a gate electrode even when using, as a gate insulating film, a material with which it is unable to have a high etching selective ratio to the first conductive layer.
With the method of the third or eleventh aspect, a semiconductor is expanded by the oxidation in the step (d). Therefore, the ion implantation for forming an extension region is facilitated by performing it after the step (c) and before the step (d).
With the method of the fourth aspect, the gate electrode resistance can be lowered by using metal for the second conductive layer. The oxidization is conducted in the presence of a reducing component in the step (d), thus preventing the second conductive layer composed of metal from being oxidized.
With the method of the seventh aspect, a semiconductor is expanded by the oxidation in the step (d). Therefore, the ion implantation for forming an extension region is facilitated by performing it after the step (f) and before the step (d).
With the method of the eighth aspect, the gate electrode resistance can be lowered by using metal for the second conductive layer. It is able to prevent the second conductive layer composed of metal from being oxidized, because the silicide layer formed in the step (g) functions as a mask against oxidization.
With the method of the ninth aspect, the first conductive layer is not etched, however, with a dummy gate acting as a mask, this layer is left only below the dummy gate by imparting insulating property in a self-aligned manner. The third conductive layer provided in a recess formed at the area where the dummy gate has been present, and also the first conductive layer left below the third conductive layer, cooperate in functioning as a gate electrode. It is therefore able to reliably form a gate electrode even when using, as a gate insulating film, a material with which it is unable to have a high etching selective ratio to the first conductive layer.
With the method of the tenth aspect, the first insulating layer and gate insulating film are etched in the step (j). This enables to reliably form a gate electrode even when using, as a gate insulating film, a material with which it is unable to have a high etching selective ratio to the first conductive layer.
With the method of the twelfth aspect, the lower portion of the end of the conductor has insulating property, thereby providing superior insulation between the source/drain regions and the gate electrode which is formed by the conductor and the portion of the interposing layer which has a conductivity.
It is an object of the present invention to provide a technique of permitting a reliable formation of a gate electrode even when using, as a gate insulating film, a material, e.g., a nitride film, with which it is unable to have a high etching selective ratio to polysilicon.